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Fer­ro­electric Memory GmbH (FMC) - Semi­con­duc­tors

We are a spin-off from TU Dres­den com­mer­cia­li­zing a novel non­vo­la­tile memory tech­no­logy. We col­la­bo­rate with cut­ting edge semi­con­duc­tor com­pa­nies to bring both our memory tech­no­logy and our memory IC designs to various cust­o­m­ers world­wide.

Mixed-Sig­nal Design Veri­fic­a­tion Engin­eer (m/f)

Work­ing field:

You will be respons­ible for the veri­fic­a­tion of FeFET memory IC designs and build­ing blocks. You will work in close col­lab­or­a­tion with our design and char­ac­ter­iz­a­tion teams and your tasks will include:

  • Devel­op­ment of veri­fic­a­tion plans
  • Devel­op­ment of an effi­cient and reusable veri­fic­a­tion envir­on­ment
  • Devel­op­ment and integ­ra­tion of top-level and mod­ule-level test benches
  • Defin­i­tion and imple­ment­a­tion of test cases
  • Devel­op­ment and integ­ra­tion of veri­fic­a­tion IPs
  • Act­ive par­ti­cip­a­tion in SOC test devel­op­ment and debug

Require­ments:

  • M.Sc. / M.Eng. or higher in elec­trical engin­eer­ing
  • > 5 years exper­i­ence in ana­log/mixed-sig­nal veri­fic­a­tion
  • Know­ledge of dif­fer­ent veri­fic­a­tion meth­od­o­lo­gies
  • Famili­ar­ity with industry-stand­ard design and sim­u­la­tion tools (e.g. Cadence® DFII)
  • Good tech­nical com­pre­hen­sion
  • Strong prob­lem solv­ing abil­ity
  • Abil­ity to work in a team envir­on­ment
  • Interest in work­ing in a start-up envir­on­ment

What we of­fer:

Com­pet­it­ive salary will be based on a com­bin­a­tion of fixed salary and yearly bonus pay­ments.

How to ap­ply:

For fur­ther inform­a­tion please con­tact:

Fer­ro­elec­tric Memory GmbH
Attn.: Marko Noack
Noeth­nitzer Str. 64
Dresden, Ger­many

T +49 178 1666185
marko.noack@ferroelectric-memory.com